1. Field of the Invention
The present invention relates to a semiconductor integrated memory circuit, and particularly to a device for trimming variation in threshold voltage of a latch circuit. Moreover, the present invention relates to a trimming method of the threshold voltage using such a device.
2. Description of the Related Art
An access speed of a semiconductor integrated memory circuit such as SRAM is greatly affected by the operation speed of the sense amplifier, as well as by the operation speed of the memory cell. The sense amplifier generally employs a structure with MOS transistors, from the viewpoint of low power consumption. The sense amplifier comprises a latch circuit constructed by MOS transistors.
However, the semiconductor memory element having a sense amplifier composed of MOS transistors has a large variation in threshold voltage of the sense amplifier. Also, the operation of the sense amplifier is delayed until the signal levels on the bit line increase larger than an offset thereof. This is regarded as a problem of such a semiconductor memory device. Moreover, a latch circuit formed of MOS transistors is included in an SRAM cell. An offset in such the latch circuit may affect the reading speed.
The following method has been proposed to solve the above-mentioned problem. That is, in a known method, a means for trimming an offset is introduced in the semiconductor integrated memory circuit, and a voltage suitable for the amount of trimming is applied to the MOS transistors included in the sense amplifier circuit. This method is described in JP 10-162585A. However, the method requires a trimming means and trimming adjustment unit to be formed in the device in addition to the sense amplifier. This increases the area of the semiconductor integrated memory circuit. In addition, this method is advantageous because trimming suitable for the offsets of plural sense amplifiers. However, it takes a lot of time to finish trimming for all the sense amplifier circuits or the like in the semiconductor integrated memory device because it requires adjustment for respective sense amplifier circuits.
Therefore, the conventional art has difficulty in providing a semiconductor integrated memory circuit that may trim the offset of the sense amplifier circuit with high efficiency while requiring a smaller area.